library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_bit.all;

entity randomico is
    generic ( width : integer :=  5 ); 
port (
      clk : in bit;
      --random_num : out std_logic_vector (width-1 downto 0)   --output vector   
		random_num : out integer
    );
end entity;

architecture Behavioral of randomico is
begin
	process(clk)
		variable rand_temp : bit_vector(width-1 downto 0):=(width-1 => '1',others => '0');
		variable temp : bit := '0';
	begin
		if(rising_edge(clk)) then
			temp := rand_temp(width-1) xor rand_temp(width-2);
			rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
			rand_temp(0) := temp;
		end if;
		random_num <= to_integer(unsigned(rand_temp));
	end process;
	
end architecture;